(1) Field of the Invention
This invention relates to an apparatus and method for chemical/mechanical polishing (CMP) a semiconductor substrate and more particularly to an apparatus and method for simulating CMP conditions in order to efficiently study the behavior of CMP processes while varying process parameters.
(2) Description of Related Art
Chemical-mechanical polishing (CMP) has been developed for providing smooth topographies on surfaces deposited on semiconductor substrates. Rough topography results when metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have a smooth topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces. CMP can, also, be used to remove different layers of material from the surface of a semiconductor substrate. For example, following via hole formation in an insulating layer, a metallization layer is deposited and then CMP is used to produce planar metal studs embedded in the insulating layer.
Briefly, the CMP processes involve holding and rotating a thin, flat wafer of the semiconductor material against a wetted polishing surface under controlled chemical, pressure, and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch various surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
Numerous process parameters affect the polishing results. Process parameters include polish slurry composition, polish slurry temperature, polish pad material, rotation speed of the polish pad, rotation speed of the wafer carrier, pressure between the wafer carrier and polish pad, and polish time. Also, the use history of the polish pad and the rate of dispensing the polish slurry can affect the polishing results. In addition, the polishing results are dependent on the material being polished, the initial topography of the substrate, and the distribution of topographic pattern density and feature size. Due to the multiplicity of parameters which affect the polishing result and the possibility of complex interaction between parameters, development of CMP processes is time consuming and costly. Usual practice is to use monitor wafers to measure polishing results. Processing of monitor wafers for each process parameter change is costly and time consuming. Also, since monitor wafers are measured off-line, there is considerable time delay in ascertaining the result of a change in process parameters on the polishing process. The inability to readily predict the impact of process parameter changes on the performance of CMP frustrates process development.
While numerous improved CMP methods have been developed as shown in the following U.S. Patents, these methods result only after expenditure of considerable time and resource. U.S. Pat. No. 5,032,203 entitled "Apparatus For Polishing" granted Jul. 16, 1991 to Toshiroh K. Doy et al describes an improved polishing method and apparatus in which a pad conditioning ring containing metallic elements is employed to improve polishing efficiency. U.S. Pat. No. 5,320,706 entitled "Removing Slurry Residue From Semiconductor Wafer Planarization" granted Jun. 14, 1994 to Robert E. Blackwell describes a method and apparatus for chemical/mechanical polishing (CMP) in which, following the polishing step, residual slurry polish residue is removed by polishing with a mixture of deionized water and a surfactant.
The present invention is directed to a novel method and apparatus for simulating CMP processes.